The fix was insane but simple: drill a tiny hole through the overlapping region to break the capacitive coupling, then backfill with non-conductive epoxy. It took three hours of microsurgery under a stereo microscope. When they powered up the board again, C442 stayed cold. The 3.3V rail held steady.
Dev leaned in. On the boardview, the two planes showed as overlapping translucent shapes, creating a muddy brownish color. He’d always assumed that was a rendering artifact.
“The boardview wasn’t wrong,” Maya said, sitting back. “It was telling us the truth. We just didn’t know how to read it.”
“Or,” Maya said, a new thought crystallizing, “the boardview is right, and we’re misreading the layer stack-up.”
Maya saved the boardview file one last time. In the REV_NOTES field, she added a new line: “Hole drilled at D-17. Dielectric thickness critical. The map had the secret—you just had to believe it was there.”
“Unless,” Maya said, pulling up the physical board and a microscope, “the dielectric between inner1 and inner2 on this particular batch was mis-specified. The fab house used a prepreg that’s half the required thickness.” She pointed to region D-17 on the boardview. “Look. Right under C442’s shadow. The 3.3V plane on inner1 and the GND plane on inner2 aren’t just overlapping—they’re perfectly aligned for a two-centimeter square.”
Maya grabbed a razor blade and carefully delaminated a corner of the PCB near D-17. Under the microscope, the cross-section was undeniable: inner1 and inner2 were separated by a gossamer-thin layer of fiberglass, not the standard 0.8mm. They were practically touching.